Hazard3

I think the GP is talking about the Hazard3 [1] core. This is one of the CPU cores besides the ARM M33 instantiated on the RP2350 µC [2]. See this article from Luke Wren (Wren6991) back when the RP2350 came out [3]. [1] https://github.com/Wren6991/Hazard3 [2] https://www.raspberrypi.com/products/rp2350/ [3] https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico...

Indeed https://github.com/Wren6991/Hazard3

It's an open source core design [0], so pretty open. [0] https://github.com/Wren6991/Hazard3

The Hazard 3 is basically a hobby project of Luke Wren, a Raspberry Pi Employee. He's contiuing to evolve it further, but I don't think it's ready for a full replacement of the Cortex-M yet, especially in regards to the Security Features. The source code is all from Luke Wren and I don't think other cores use the source code directly, but improvements to test harnesses or general implementation patterns as well as better software support help other cores: https://github.com/Wren6991/Hazard3 For the SoCs I would expect to see an off-the-shelf Risc-V core (certainly no Hazard3 as the main CPU), but we'll see.

This. SiFive, for example, is a proprietory core design based on the open source RISC V spec. Hazard3 [0] on the other hand, is an open source core design. [0] https://github.com/Wren6991/Hazard3

https://github.com/Wren6991/Hazard3 this one is well tested in real life and works well (it is the RV core in RP2350)

It is funny that you should say that, considering that I was wondering this myself earlier today WRT the Hazard3 cores in the RP2350. It turns out someone did benchmarks: https://icircuit.net/benchmarking-raspberry-pi-pico-2/3983 The Hazard3 core was designed by a single person while the ARM Cortex cores were presumably designed by a team of people. The Hazard3 cores mostly outperforms the Cortex-M0+ cores in the older RP2040 and are competitive with the Cortex-M33 cores that share the RP2350 silicon. For integer addition and multiplication, they actually outperform the Cortex-M33 cores. Before you point out that they lost most of the benchmarks against the Cortex-M33 cores, let me clarify that the integer addition and multiplication performance matter far more for microcontrollers than the other tests, which is why I consider them to be

RP2350 (Raspberry Pi Pico 2) has two Hazard3 cores, which is open-source at: https://github.com/Wren6991/Hazard3

How is the problem of "you signed a CLA without authorization by your employer to do so" solved? I'm mostly asking because I saw the following: "I will not expose people taping out Hazard3 to the possibility of your employer chasing you for your contribution by harassing them legally. A contribution agreement does not solve this, because you may sign it without the legal capability to do so (...)" https://github.com/Wren6991/Hazard3/blob/stable/Contributing... (this is I believe the repo with design for riscv cores running on RPi Pico 2)

None of this is new. None of it. In fact, bitfield extract is such an obvious oversight that it is my favourite example of how idiotic the RISCV ISA is (#2 is lack of sane addressing modes). Some of the better RISCV designs, in fact, implement a custom instr to do this, eg: BEXTM in Hazard3: https://github.com/Wren6991/Hazard3/blob/stable/doc/hazard3....

The author is also the creator of the RISC-V core found in the RP2350, you don't get your own core design taped out as an ASIC and then not show it off :p https://github.com/Wren6991/Hazard3

See https://github.com/Wren6991/Hazard3/tree/stable/test for the test harnesses used. I wonder if they did release all they used there.

Hazard3 pointer https://github.com/Wren6991/Hazard3 I think it's cool as a cucumber that we can choose fully open-source RISC-V if we want. My guess is the RV cores are slower clock-per-clock than the M33 cores; that is benchmark scores for M33's will be better, as Hazard3 is only 3-stage pipeline - but so is M33. Can't wait for the benchmarks.

This looks awesome a really great step up from the RP2040. I'm a big fan of the original and I'm excited to see all the improvements and upgrades. I imagine with the new secure boot functionality they've got a huge new range of customers to tempt to. Also exciting to see them dip their toe into the open silicon waters with the hazard 3 RISCV core https://github.com/Wren6991/Hazard3. Of course it they'd used Ibex https://github.com/lowrisc/ibex the RISC-V core we develop and maintain at lowRISC that would have been even better but you can't have everything ;)