coreboot

On x86 the cache is implicit when you touch memory, and there are many ISA ops (push, call, ...) that implicitly update stack memory. But if you never call those, it is possible to access the cache explicitly. Coreboot have a custom in-tree compiler, ROMCC [1] that compiles C to a subset of x86 that never emits memory operations. They use this to treat cache as RAM [2] for a brief period during early boot before the RAM itself gets initialized. 1. https://github.com/wt/coreboot/tree/master/util/romcc The whole compiler is a single C file 2. https://www.coreboot.org/data/yhlu/cache_as_ram_lb_09142006.... Perform s/LinuxBIOS/Coreboot/ in your head as you read

> It's responsible for initialising the chip and getting it out of bed enough to the point where at least one of the main cores can run using cache-as-RAM mode The somewhat surprising but true implication is that on boot, the CPU is initialized before the RAM is initialized. So there is a window of time during boot when the main core on the CPU is running instructions that cannot access the RAM. Even on register-starved x86 it is possible to write code without using RAM, but it certainly seems more convenient to me to treat the cache as RAM. Documentation for a special compiler that compiles to code that doesn't use RAM: https://github.com/wt/coreboot/blob/master/util/romcc/romcc....