nanotube

With the chiplet future here, some interconnect expertise should really really help all the chips. Hoping to heck we see AMD not rest on the laurels & get good at CXL, start offering on chip UCE Ethernet and UALink interconnect. Also would really like to see on-package USB4 80Gbps; AMD really lead the way with getting good at IO and allowing users to reuse lanes as either PCIe or SATA or uh what was that third... Continuing to offer robust io is something Xilinx folks should be excellent at. And yeah they should hopefully have a significant cellular revenue stream too! Grow that! It was neat seeing Lattice stop by the OCP EvenStar mailing list to promote their fpgas. Would be great to see similar outreach of Xilinx making visible motions to connect with & be in sync with our planet's better open source cellular efforts too. https://ocp-al

Decade and a half ago there was PacketShader, which used usermode networking+GPUs to do packet routing. It was a thrilling time. I thought this kind of effort to integrate off-the-shelf hardware and open source software-defined-networking (SDN) was only going to build and amplify. We do have some great SDN but remains a fairly niche world that stays largely behind the scenes. https://shader.kaist.edu/packetshader/index.html I wish someone would take up this effort again. It'd be awesome to see VPP or someone target offload to GPUs again. It feels like there's a ton of optimization we could do today based around PCI-P2P, where the network card could DMA direct to the GPU and back out without having to transit main-memory/the CPU at all; lower latency & very efficient. It's a long leap & long hope, but I very much dream that CXL eventually