thead-extension-spec

> indexed addressing Ok, this time I have a proper benchmark. The XuanTie C910 core supports a custom extension with indexed loads [0] and I got my access to a MILK-V Pioneer server with that CPU working again. As a quick benchmark I used a self compile of the chibicc C compiler: https://godbolt.org/z/4MMxsEarE Measuring with the equivalent of rv64gcb and rv64gcb_xtheadmemidx, the xtheadmemidx variant ended up about 0.3% faster on the same core. [0] https://github.com/XUANTIE-RV/thead-extension-spec/blob/mast...

> Well, lack of REG+REG and REG+SHIFTED_REG addressing modes handicaps it significantly. Does it? Well, there's a vendor specific extension for that (XTheadMemIdx): https://github.com/XUANTIE-RV/thead-extension-spec/releases/... Not sure about GCC, but on clang it is trivial to enable it. And if you really want to (assuming you have the hardware) you could compile exactly the same code with and without it and compare how much exactly it is handicapped if those instructions are not there. Plus, on RISC-V multiplication/division (about which you've complained) is optional, and there is also a variant of RISC-V with only 16 registers instead of 32 (also very simple to enable on recent versions of clang, although Linux would probably need some modifications to be able to run on that). So I'm not entirely convinced that RISC-V would be worse h

"Real truth" and "fan boys"? Let's have some facts: there are indeed a boatload of extensions, though perhaps not (yet) to the V extension itself. T-HEAD [1], Ventana's ternary op [2], Sifive also has a couple [3], including "Xsfvfwmaccqqq", one of at least four completely different matmul variants. In particular for the latter, I would say fragmentation is an absolutely valid concern at the moment. [1]: https://github.com/T-head-Semi/thead-extension-spec [2]: https://github.com/ventanamicro/ventana-custom-extensions/re... [3]: https://www.sifive.com/documentation

TH1520 (and SG2042, D1) have THead custom extension that contains a lot of the same things as Zba and Zbb, just slightly different and with encodings in the custom opcode spaces. e.g. "th.addsl rd, rs1, rs2, imm2" which has an immediate field for the shift instead of separate instructions (which is just documentation really), and shifts rs2 while Zba's sh1add, sh2add, sh3add shift rs1. Also th.ff0, th.ff1, th.rev, th.tstnbz (same as orc.b but with inverted result) They also have pre- and post-increment loads and stores with writeback of the incremented pointer, and [rs1 + rs2 << imm2] loads and stores, which can be useful for JITing x86 (or ARM) addressing modes. https://github.com/T-head-Semi/thead-extension-spec/releases...