nextpnr

That's why nextpnr exists :) https://github.com/YosysHQ/nextpnr As someone actively working on nextpnr support for a fairly new FPGA architecture, it really is amazing that we have something like that in the open source world. YosysHQ are one of my favorite companies to exist.

Wondering how this compares to nextpnr (https://github.com/YosysHQ/nextpnr) ?

If the name were an arbitrary word which didn't attempt to define itself, would that be any better? I don't see why the name must mean anything specific, nor why you should expect the name to explain what the project is. That's what the documentation or other descriptive text is for. That the name gives some understanding at first glance is a bonus. PnR is "place and route", and is a very common acronym in the ASIC/FPGA/VLSI space. It seems fair to expect those who'd use this specialized variant of Yosys to also be familiar with PnR. For reference, here's [1] Yosys's PnR tool, which expands the acronym in its README title. Realistically, if you're using Yosys tools, you're going to need to have some familiarity with the underlying flows anyway; in my experience they're very powerful but also pretty DIY. That's not great, but it's the real

full disclosure: I work for YosysHQ, who have an alternative open-source place-and-route program - [nextpnr](https://github.com/YosysHQ/nextpnr/) - and YosysHQ presently has [a grant](https://activities.esa.int/4000141380) from ESA on improving nextpnr. to be blunt: nextpnr is what happens when you look at VPR as prior art and base every design decision around doing the opposite of VPR. VPR is flexible, true: you can define an architecture description inside an XML file, but I view the VPR XML format to be poorly considered. - commonly in an FPGA you will have "legality constraints" - for example, a block of LUTs cannot simultaneously be in carry-chain mode and act as LUT RAM. to produce a legal solution, all these constraints must be satisfied. to nextpnr this is [two basic](https://github.com/YosysHQ/nextpnr/blob/master/docs/archapi....

Look up the boards that use the Lattice ECP5 chips, I think these are the largest FPGAs that have a fully open toolchain: https://github.com/YosysHQ/nextpnr You'd need to learn some digital design for any FPGA board. I recommend the book "Digital Design and Computer Architecture" by David and Sarah Harris.

this is true in general but 1) vivado webpack edition (ie free) lets you write (and flash) a bitstream for some of the small chips. i know it at least works for the artix-7 family because i'm doing it every day lately 2) for the artix-7 (and some lattice chips) you supposedly can use OSS (https://github.com/SymbiFlow/prjxray). i haven't tried it yet but one problem i can foresee is that the OSS tools won't infer stuff like brams and dsp. in fact the symbiflow people (i think?) explicitly call this out as the part of the project that's a work in progress. some useful links: https://arxiv.org/abs/1903.10407 https://github.com/YosysHQ/nextpnr https://www.rapidwright.io/

https://hdl.github.io/awesome/items/vpr/ https://github.com/YosysHQ/nextpnr

There has been significant progress in reverse engineering bitstream formats of some FPGAs which has allowed the development of open source FPGA workflows. If you want to know more, take a look at: Icestorm http://www.clifford.at/icestorm/ Yosys http://www.clifford.at/yosys/ NextPNR https://github.com/YosysHQ/nextpnr SymbiFlow https://symbiflow.github.io/

For simulation and formal verification, yes, absolutely. Either Icarus Verilog, Verilator or SymbiYosys have been used for large commercial designs. For synthesis, the only FPGAs families currently supported by an open source flow are the Lattice iCE40 and ECP5 [0]. The latter is something you can be decently productive with and can fit quite a bit of logic (think: Amiga reimplementation, PCIe interfacing, etc.). If you'd like to port synthesizeable code from the open source world to the commercial world, this _should_ just work as long as you're willing to rewrite any physical interfacing code (since those depend on hardware blocks available in a particular family) and stick to high-quality Verilog. But that's the same as porting across any other FPGA families. Disclaimer: I work with SymbioticEDA, who develop and provide commercial supp

Verilator is an awesome tool. I suggest if you are interested in open-source EDA this you also check out Icarus Verilog [1] - an event based Verilog sim, Yosys [2] - a Verilog synthesis tool and formal solver, and NextPNR [3] - a place-and-route tool. The set of these provide a pretty reasonable set of tools for developing hardware (that is HDL) with fully open source software! [1] - http://iverilog.icarus.com/ [2] - http://www.clifford.at/yosys/ [3] - https://github.com/YosysHQ/nextpnr

Yes, for the Lattice iCE40 and ECP5 families: https://github.com/YosysHQ/nextpnr

The site is actually a bit out of date, the ECP5 bit (Project Trellis) and nextpnr are already working: https://github.com/YosysHQ/nextpnr