picorv32

Development status This project is no longer under active development. Formal verification of the core is possible with the RISC-V Formal Verification Framework. Please direct any questions to the official YosysHQ Discourse. PicoRV32 - A Size-Optimized RISC-V CPU PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained from the RISC-V GNU toolchain (see the build instructions below). The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. Many Linux distributions now include the tools for RISC-V (for example Ubuntu 20.04 has gcc-riscv64-unknown-elf). To compile using those set TOOLCHAIN_PREFIX accordingly (eg. make TOOLCHAIN_PREFIX=riscv64-unknown-elf-). PicoRV32 is free and open hardware licensed under the ISC license (a license that is similar in terms to the MIT license or the 2-clause BSD license). Table of Contents Features and Typical Applications Files in this Repository Verilog Module Parameters Cycles per Instruction Performance PicoRV32 Native Memory Interface Pico Co-Processor Interface (PCPI) Custom Instructions for IRQ Handling Building a pure RV32I Toolchain Linking binaries with newlib for PicoRV32 Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs Features and Typical Applications Small (750-2000 LUTs in 7-Series Xilinx Architecture) High fmax (250-450 MHz on 7-Series Xilinx FPGAs) Selectable native memory interface or AXI4-Lite master Optional IRQ support (using a simple custom ISA) Optional Co-Processor Interface This CPU is meant to be used as auxiliary processor in FPGA designs and ASICs. Due to its high fmax it can be integrated in most existing designs without crossing clock domains. When operated on a lower frequency, it will have a lot of timing slack and thus can be added to a design without compromising timing closure. For even smaller size it is possible disable support for registers x16..x31 as well as RDCYCLE[H], RDTIME[H], and RDINSTRET[H] instructions, turning the processor into an RV32E core. Furthermore it is possible to choose between a dual-port and a single-port register file implementation. The former provides better performance while the latter results in a smaller core. Note: In architectures that implement the register file in dedicated memory resources, such as many FPGAs, disabling the 16 upper registers and/or disabling the dual-port register file may not further reduce the core size. The core exists in three variations: picorv32, picorv32_axi and picorv32_wb. The first provides a simple native memory interface, that is easy to use in simple environments. picorv32_axi provides an AXI-4 Lite Master interface that can easily be integrated with existing systems that are already using the AXI standard. picorv32_wb provides a Wishbone master interface. A separate core picorv32_axi_adapter is provided to bridge between the native memory interface and AXI4. This core can be used to create custom cores that include one or more PicoRV32 cores together with local RAM, ROM, and memory-mapped peripherals, communicating with each other using the native interface, and communicating with the outside world via AXI4. The optional IRQ feature can be used to react to events from the outside, implement fault handlers, or catch instructions from a larger ISA and emulate them in software. The optional Pico Co-Processor Interface (PCPI) can be used to implement non-branching instructions in an external coprocessor. Implementations of PCPI cores that implement the M Standard Extension instructions MUL[H[SU|U]] and DIV[U]/REM[U] are included in this package. Files in this Repository README.md You are reading it right now. picorv32.v This Verilog file contains the following Verilog modules: Module Description picorv32 The PicoRV32 CPU picorv32_axi The version of the CPU with AXI4-Lite interface picorv32_axi_adapter Adapter from PicoRV32 Memory Interface to AXI4-Lite picorv32_wb The version of the CPU with Wishbone Master interface picorv32_pcpi_mul A PCPI core that implements the MUL[H[SU|U]] instructions picorv32_pcpi_fast_mul A version of picorv32_pcpi_fast_mul using a single cycle multiplier picorv32_pcpi_div A PCPI core that implements the DIV[U]/REM[U] instructions Simply copy this file into your project. Makefile and testbenches A basic test environment. Run make test to run the standard test bench (testbench.v) in the standard configurations. There are other test benches and configurations. See the test_* make target in the Makefile for details. Run make test_ez to run testbench_ez.v, a very simple test bench that does not require an external firmware .hex file. This can be useful in environments where the RISC-V compiler toolchain is not available. Note: The test bench is using Icarus Verilog. However, Icarus Verilog 0.9.7 (the latest release at the time of writing) has a few bugs that prevent the test bench from running. Upgrade to the latest github master of Icarus Verilog to run the test bench. firmware/ A simple test firmware. This runs the basic tests from tests/, some C code, tests IRQ handling and the multiply PCPI core. All the code in firmware/ is in the public domain. Simply copy whatever you can use. tests/ Simple instruction-level tests from riscv-tests. dhrystone/ Another simple test firmware that runs the Dhrystone benchmark. picosoc/ A simple example SoC using PicoRV32 that can execute code directly from a memory mapped SPI flash. scripts/ Various scripts and examples for different (synthesis) tools and hardware architectures. Verilog Module Parameters The following Verilog module parameters can be used to configure the PicoRV32 core. ENABLE_COUNTERS (default = 1) This parameter enables support for the RDCYCLE[H], RDTIME[H], and RDINSTRET[H] instructions. This instructions wil