wildebeest

This sounds exciting, and the press release does a great job of explaining why. For anyone else who was wondering, it says it's under the Apache 2.0 license: https://github.com/zeroasiccorp/wildebeest?tab=Apache-2.0-1-... I didn't realize that Xilinx xc7 synthesis was officially a feature of Yosys already! Dropping the logic depth for picorv32 on LUT6s from 17 to 6 seems like it will double the achievable frequency or more. It's especially impressive that this beats the vendor tools—but it's unclear to me if this is an apples-to-apples comparison.

Documentation can be found in two places. What else do you need to know? https://github.com/siliconcompiler/logiklib/tree/main/logikl... https://github.com/zeroasiccorp/wildebeest/tree/main/archite...

I am sorry you that's how it looks...can't argue with feelings, We did everything we could to give credit. Open source SW should be a stack and every project needs a proper name as a reference. I do find the statement a bit ironic though, b/c 99% of Yosys users don't know that 99% of the logic synthesis sauce in Yosys is done by ABC. https://github.com/zeroasiccorp/wildebeest