chisel

How does this compare to chisel [1] , i never could get around the whole scala tooling - seemed a bit over the top. Though i guess it is a bit more mature and probably more enterprisey [1]https://github.com/chipsalliance/chisel

Chisel picked up Scala 3 support in 7.0.0 released last September (https://github.com/chipsalliance/chisel/releases/tag/v7.0.0), right now they cross-compile between Scala 2 and 3 but from what I heard they should eventually move to Scala 3 only to start taking advantage of new features like named tuples (https://docs.scala-lang.org/scala3/reference/other-new-featu...).

On the software front as mentioned VHDL and Verilog are showing their age with their design as well as ther tooling ecosystem.Attempts such as CHISEL[1] (written in Scala)also havent gotten much traction - seeing also the language choice - would have btter have been in something more accesible like kotlin/ocaml. Secondly the integration with consumer devices and OS is almost non-ecistant - it should really be simpler to interact with ala GPU/Network chip and have more mainboards with lowcost integrated FPGAs even if they are only a couple of hundred of logic cells. [1]https://github.com/chipsalliance/chisel/blob/main/README.md

Am I understanding the README correctly in that: You can execute some nix commands to fire up an emulator for this CPU design? That's pretty cool, I wonder how hard it'd be to reduce it to a docker command? Also, I'd never heard of Chisel but it looks amazing - software defines hardware via a Python-esque DSL to Verilog compiler. https://github.com/chipsalliance/chisel

Seems similar to the Chisel compiler for RISC-V: https://github.com/chipsalliance/chisel3

One of the Chisel/FIRRTL devs here available to answer any questions. tl;dr: Chisel/FIRRTL is trying to be "LLVM for circuits". Concretely, Chisel is a domain specific language for describing hardware in Scala. The Chisel front-end generates circuit IR (Flexible Intermediate Representation for RTL/FIRRTL), FIRRTL IR is then transformed/customized by the middle-end FIRRTL compiler, and finally emitted via a Verilog backend (and then fed into FPGA/ASIC tooling). It's not High Level Synthesis, just powerful hardware description. You get all the features of Scala (object-oriented programming, functional programming, first class functions, parametric polymorphism) to write programs that generate circuits. Sadly, the last 50 years of software engineering is traditionally not available to hardware designers in classic languages like Verilog or V

Thanks for taking a look at Chisel and FIRRTL! (Coming from a Chisel/FIRRTL dev...) Couple of clarifying comments: CDE[^1] is really a Rocket Chip[^2] specific design decision meant to suit the configuration needs of system-on-chip generation (or: it's a Scala library which actually doesn't depend on Chisel and could be useful in unrelated projects). Also, SiFive should have fixed the issues with exceptions a long while ago (stack traces are still a thing, though). Chisel gets a lot of criticism due to the (necessary) complexities of Rocket Chip. However, don't let that dissuade you from using it for a separate digital design project. None of the Rocket Chip complexity comes into play there. Compilation time is something that we really care about and are seeking to make better. Minute-long Verilog generation times are something you would

This whole story of later years, maybe it will bring more attention to the lack of progress in commercial hardware design tools, their ridiculous price, and existing efforts to create modern open source alternatives, like SymbiFlow [1], Chisel3 [2]/FIRRTL[3], The Open ROAD[4] project, etc. [1] https://symbiflow.githib.io [2] https://github.com/freechipsproject/chisel3 [3] https://github.com/freechipsproject/firrtl [4] https://theopenroadproject.org/

Quite the opposite - it makes more and more companies to consider open source. RISC-V is all rage now, people turning their eyes to open source EDAs. I hope with the help of SymbiFlow[1], Chisel[2]/FIRRTL[3], and other similar tools the duopoly of Intel (Altera) and Xilinx will come to its end. There is also an interesting initiative[4] to make ASIC design as affordable (in terms of time, knowledge, and money) as possible. And using KiCad[5] for simple projects can help for small businesses. [1] https://symbiflow.github.io/ [2] https://github.com/freechipsproject/chisel3 [3] https://github.com/freechipsproject/firrtl [4] https://theopenroadproject.org/ [5] http://kicad-pcb.org/

Hopefully, it will not only boost RISC-V adoption, but also the FOSS EDA[1][2][3] tools, FPGA[4][5] and ASIC[6][7][8] design tools, various high-level languages, and toolkits to work with hardware designs. You can also follow my idea[9] and initiative to create low-level hardware IR instead of al tools parsing or producing Verilog/VHDL. Apparently, both are a pretty bad fit for chip design, thus many high-level languages[10] were created. [1] KiCAD http://kicad-pcb.org/ [2] Qucs https://github.com/Qucs/qucs [3] gEDA http://www.geda-project.org/ [4] Yosys https://github.com/YosysHQ/yosys [5] SymbiFlow https://symbiflow.github.io [6] The OpenROAD https://theopenroadproject.org [7] The OpenROAD https://github.com/The-OpenROAD-Project [8] Chisel3 https://github.com/freechipsproject/chisel3 [9] https://github.com/SymbiFlow/ideas/issues/19 [10]

It doesn't look like you're open to any serious criticisms of the two Vs, but the readers of your comment and mine deserve to look at the arguments and make up their own mind. Therefore, I'm linking the pages regarding rationale for some of the recent HDLs: - Chisel: https://github.com/freechipsproject/chisel3/wiki/Frequently-... - MyHDL: http://www.myhdl.org/start/why.html - SpinalHDL: https://spinalhdl.github.io/SpinalDoc/regular_hdl