firrtl

> There was an attempt to make a kind of IR for RTL that would break the tie with SV It's probably FIRRTL and CIRT is the compiler for that [1], [2]. [1] The specification for the FIRRTL language: https://github.com/chipsalliance/firrtl-spec [2] Original FIRRTL compiler that's now been replaced by CIRT: https://github.com/chipsalliance/firrtl

Did any project other than Chisel make use of FIRRTL? https://github.com/chipsalliance/firrtl

I want Chisel to succeed so badly. I'm so sick and tired of writing VHDL. Verilog is no better. Also it looks like LLHD is perhaps analogous to LLVM in that they offer an intermediate representation instead of providing a language that you code in yourself. Chisel also offers this via FIRRTL [1]. I can't decide whether to be excited about the fact that there are multiple ideas in this space or frustrated that these disparate teams aren't simply collaborating. [1]: https://github.com/chipsalliance/firrtl

> I thought Berkeley's BOOM is way more advanced implementation of RISCV than VexRiscV and it is written in Chisel3. It is a lot more advanced and thus harder to get started with than VexRiscV. > BOOM does not look like most effective in terms of LUTs utilisation core. So the problem is also that the BOOM design is targeted at ASICs. The developers do not generally synthesize BOOM for FPGA. Only as a FireSim project which is using FPGAs to do fast simulations in order to get more accurate performance figures by running real world benchmarks (multiple MHz of target frequency). None of the developers are interested in using BOOM as a computer on an FPGA and thus no one has provided support for that. > Another thing I also disliked in Chisel3 is dependancy on new intermediate representation of hardware (FIRRTL) which adds one more layer of a

One of the Chisel/FIRRTL devs here available to answer any questions. tl;dr: Chisel/FIRRTL is trying to be "LLVM for circuits". Concretely, Chisel is a domain specific language for describing hardware in Scala. The Chisel front-end generates circuit IR (Flexible Intermediate Representation for RTL/FIRRTL), FIRRTL IR is then transformed/customized by the middle-end FIRRTL compiler, and finally emitted via a Verilog backend (and then fed into FPGA/ASIC tooling). It's not High Level Synthesis, just powerful hardware description. You get all the features of Scala (object-oriented programming, functional programming, first class functions, parametric polymorphism) to write programs that generate circuits. Sadly, the last 50 years of software engineering is traditionally not available to hardware designers in classic languages like Verilog or V

Thanks for taking a look at Chisel and FIRRTL! (Coming from a Chisel/FIRRTL dev...) Couple of clarifying comments: CDE[^1] is really a Rocket Chip[^2] specific design decision meant to suit the configuration needs of system-on-chip generation (or: it's a Scala library which actually doesn't depend on Chisel and could be useful in unrelated projects). Also, SiFive should have fixed the issues with exceptions a long while ago (stack traces are still a thing, though). Chisel gets a lot of criticism due to the (necessary) complexities of Rocket Chip. However, don't let that dissuade you from using it for a separate digital design project. None of the Rocket Chip complexity comes into play there. Compilation time is something that we really care about and are seeking to make better. Minute-long Verilog generation times are something you would

This whole story of later years, maybe it will bring more attention to the lack of progress in commercial hardware design tools, their ridiculous price, and existing efforts to create modern open source alternatives, like SymbiFlow [1], Chisel3 [2]/FIRRTL[3], The Open ROAD[4] project, etc. [1] https://symbiflow.githib.io [2] https://github.com/freechipsproject/chisel3 [3] https://github.com/freechipsproject/firrtl [4] https://theopenroadproject.org/

Yes, but LLVM is not very suitable in general for FPGA/ASIC design. FIRRTL[1][2] looks much more complete and fit among various alternatives. [1] https://bar.eecs.berkeley.edu/projects/firrtl.html [2] https://github.com/freechipsproject/firrtl

Quite the opposite - it makes more and more companies to consider open source. RISC-V is all rage now, people turning their eyes to open source EDAs. I hope with the help of SymbiFlow[1], Chisel[2]/FIRRTL[3], and other similar tools the duopoly of Intel (Altera) and Xilinx will come to its end. There is also an interesting initiative[4] to make ASIC design as affordable (in terms of time, knowledge, and money) as possible. And using KiCad[5] for simple projects can help for small businesses. [1] https://symbiflow.github.io/ [2] https://github.com/freechipsproject/chisel3 [3] https://github.com/freechipsproject/firrtl [4] https://theopenroadproject.org/ [5] http://kicad-pcb.org/

Would have been awesome if they joined the effort of developing FIRRTL[1][2] and using it as a universal (LLVM-alike) hardware intermediate language, better suited modern chip design needs than Verilog or VHDL[3]. [1] https://github.com/freechipsproject/FIRRTL [2] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/... [3] https://github.com/SymbiFlow/ideas/issues/19

Speaking about design challenges - it would be nice if industry will switch to LLVM-like low-level HDL (or RTL) language, that will allow easier cross-tool integration. So far every project implements everything itself. There is an idea[1] to adapt FIRRTL[2][3] for this needs. Here is a good paper[4] describing its features. Apparently Intel also using it, at least in the research labs. This will help to integrate all parts of FPGA and ASIC design pipeline together. For now chip-design feels like programming in 1990 - quality of tooling is very bad. [1] https://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/freechipsproject/FIRRTL [4] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/...

A bit of unrelated, but since it is important for chips development posting it here. There is an initiative [1] to make FPGA/ASIC design tooling more universal and interconnected with sharing the LLVM-like low level intermediate representation (HDL), which is more powerful than Verilog or VHDL. At this point many people see FIRRTL[2][3] as a viable candidate for this position, with some enhancements. [1] https://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/freechipsproject/FIRRTL