ideas

There is a nice discussion[1] about the same in SymbiFlow[2]. I hope, they at least read through it. [1] https://github.com/SymbiFlow/ideas/issues/19 [2] https://symbiflow.github.io/

There was a suggestion[1] (by me) to coordinate more between various hardware design/programming tools to agree on the common intermediate representation. Sadly, nothing came out of it yet. [1] https://github.com/SymbiFlow/ideas/issues/19

See also the list from my low-level hardware description language unification idea[1]. There are mostly active projects. [1] https://github.com/SymbiFlow/ideas/issues/19

The biggest pain point of "programming" hardware is the vendor tools. Imagine if all modern languages from Swift to Rust, from Python to Fortran, will all compile to C. The same situation is with HDLs - most of them compile to Verilog (some to VHDL). The world needs an open standard to rule them all - low-level HDL IR, that like LLVM can give birth to the endless variations of the cool languages, while giving them all flexibility they need. The synthesizing part would have to be written only once too. I proposed joining efforts[1] on building such a language either from scratch or based on something existing. [1] https://github.com/SymbiFlow/ideas/issues/19

And the repositories[1] themselves. You can also help them with the code - see the bunch of ideas[2] for the project. [1] https://github.com/SymbiFlow [2] https://github.com/SymbiFlow/ideas/issues

The problem of FPGAs is their proprietary nature, and Verilog/VHDL are far from the best languages. Gladly there is a number of open-source projects aiming to close this gap - Yosys[1], SymbiFlow[2], Chisel3[3]/FIRRTL[4]. Some time ago I suggested[5] different open source projects should unite and reuse the common intermediate language, akin to LLVM in many software development and analysis tools. From my point of view, FIRRTL is the best designed one, there is a huge problem of being implemented in Scala though, especially for C/C++/etc written projects. Hopefully, there will be more collaboration one day. Either reimplementation from scratch, e.g. in Rust or C++, or using Scala Native. [1] https://github.com/YosysHQ [2] https://symbiflow.github.io/ [3] https://www.chisel-lang.org/ [4] https://www.chisel-lang.org/firrtl/ [5] https://gith

Problem with Verilog and VHDL is widely known. This is why I proposed[1] to create a unified LLVM-like framework to prevent many projects from reinventing the wheel, and be able to use each other's results. [1] https://github.com/SymbiFlow/ideas/issues/19

Hopefully, it will not only boost RISC-V adoption, but also the FOSS EDA[1][2][3] tools, FPGA[4][5] and ASIC[6][7][8] design tools, various high-level languages, and toolkits to work with hardware designs. You can also follow my idea[9] and initiative to create low-level hardware IR instead of al tools parsing or producing Verilog/VHDL. Apparently, both are a pretty bad fit for chip design, thus many high-level languages[10] were created. [1] KiCAD http://kicad-pcb.org/ [2] Qucs https://github.com/Qucs/qucs [3] gEDA http://www.geda-project.org/ [4] Yosys https://github.com/YosysHQ/yosys [5] SymbiFlow https://symbiflow.github.io [6] The OpenROAD https://theopenroadproject.org [7] The OpenROAD https://github.com/The-OpenROAD-Project [8] Chisel3 https://github.com/freechipsproject/chisel3 [9] https://github.com/SymbiFlow/ideas/issues/19 [10]

Both Verilog and VHDL are a poor fit for chip design. This is why there are so many projects of higher-level hardware description languages. Chisel[1] looks to me as the best one. What I particularly like - they created an intermediate language FIRRTL[2], which might become an LLVM of hardware design. While the exact syntax might be opinionated and we need different options, the fewer wheels reinvented - the better. So at some point, it is important to create the low-level framework, on top of which many different languages can be built. You can read discussion about this particular idea here[3]. [1] https://chisel.eecs.berkeley.edu/ [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/SymbiFlow/ideas/issues/19

This is why the suggestion to create language/tooling neutral intermediate representation, based on FIRRTL[1]. [1] https://github.com/SymbiFlow/ideas/issues/19

Would have been awesome if they joined the effort of developing FIRRTL[1][2] and using it as a universal (LLVM-alike) hardware intermediate language, better suited modern chip design needs than Verilog or VHDL[3]. [1] https://github.com/freechipsproject/FIRRTL [2] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/... [3] https://github.com/SymbiFlow/ideas/issues/19

Speaking about design challenges - it would be nice if industry will switch to LLVM-like low-level HDL (or RTL) language, that will allow easier cross-tool integration. So far every project implements everything itself. There is an idea[1] to adapt FIRRTL[2][3] for this needs. Here is a good paper[4] describing its features. Apparently Intel also using it, at least in the research labs. This will help to integrate all parts of FPGA and ASIC design pipeline together. For now chip-design feels like programming in 1990 - quality of tooling is very bad. [1] https://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/freechipsproject/FIRRTL [4] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/...

A bit of unrelated, but since it is important for chips development posting it here. There is an initiative [1] to make FPGA/ASIC design tooling more universal and interconnected with sharing the LLVM-like low level intermediate representation (HDL), which is more powerful than Verilog or VHDL. At this point many people see FIRRTL[2][3] as a viable candidate for this position, with some enhancements. [1] https://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/freechipsproject/FIRRTL