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f4pga
prjtrellis
Python2018–2021
f4pga / prjtrellis

prjtrellis

Documenting the Lattice ECP5 bit-stream format.

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5Distinct people
6Mentions
0Explicit recommenders
62GitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

Documenting the Lattice ECP5 bit-stream format.

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

Mentioned in the same Hacker News threads. That is not proof they are substitutes.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:56:07 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year6 dated mentions

Observed mentions: 2018-11-20 03:43:35 UTC to 2021-09-28 13:27:32 UTC.

01232018-01-01 00:00:00 UTC to 2019-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments20182019-01-01 00:00:00 UTC to 2020-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments20192020-01-01 00:00:00 UTC to 2021-01-01 00:00:00 UTC (exclusive): 3 mentions; 0 submissions, 3 comments2021-01-01 00:00:00 UTC to 2022-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2021

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20182018-01-01 00:00:00 UTC2019-01-01 00:00:00 UTC101
20192019-01-01 00:00:00 UTC2020-01-01 00:00:00 UTC101
20202020-01-01 00:00:00 UTC2021-01-01 00:00:00 UTC303
20212021-01-01 00:00:00 UTC2022-01-01 00:00:00 UTC101

What Hacker News says

6 sources
1MachineElf·Sep 28, 2021
Would LLVM be a better comparison? The GPL'd GNU Compiler Collection (GCC) may be an inaccurate comparison given that nearly all this project's pinned GitHub repos use the ISC license: https://github.com/SymbiFlow/symbiflow-examples/blob/master/... https://github.com/SymbiFlow/symbiflow-docs/blob/master/COPY... https://github.com/SymbiFlow/icestorm/blob/master/COPYING https://github.com/SymbiFlow/prjxray/blob/master/LICENSE https://github.com/SymbiFlow/prjtrellis/blob/master/COPYING (MIT)
In Symbiflow: The GCC of the FPGA World
jhallenworld·Mar 2, 2020
RISC-V is interesting for Lattice ECP5 specifically. I'm working on a project now where I'm using it (I will make a blog or videos about it at some point): - ECP5 is the lowest cost medium size FPGA. Usually I would say that using a soft core is a waste of money vs. an external microcontroller unless you need to save space, but the cost of the added gates (say the next larger FPGA size than what you would need for a design without the soft core) is less than the cost of a microcontroller for the case where you are using ECP5 and you need video (a non-video micro is still cheaper). - Mico32 is Lattice's soft core solution. You can argue about its quality, but the very stupid reason that I prefer RISC-V is that the Mico32 tool chain does not work in Ubuntu (or at least not without a lot of work- it is supposed to work in RedHat). A lot
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of other people complain about Mico32 because it will not run Linux, but this is not so much of an issue for my design. - PicoRV32 is designed for high clock speed. This is probably not good for its own performance (multiple cycles per instruction), but it does mean that the RISC-V core is not the limiting factor for the rest of your FPGA design. https://github.com/cliffordwolf/picorv32 - The barrier to entry is low (as long as you already know GCC linker scripts). The problem with NIOS-II and especially Xilinx Microblaze is that the their tools are not simple. There is a payoff for learning their tools, in that a lot of vendor cores become available. But if you don't need the vendor cores, then the non-existent toolchain (there is no system building to learn) for RISC-V is better. An example of this is the following project trellis (a cool open source FPGA toolchain, but that's another story) example design: https://github.com/SymbiFlow/prjtrellis/tree/master/examples...
In Open Source Hardware: The Rise of RISC-V
jhallenworld·Jan 2, 2020
I just tried the Project Trellis open source FPGA tool chain for RISC-V. I was forced into it: a few years ago I bought the Lattice ECP5-5G Versa Dev kit (on sale at the time for $99, $200 now I think). The Lattice tools for the FPGA on this board requires a license. Well the license ran out, and I don't want to pay $900 for a Diamond license. Anyway, I got this example from Project Trellis to work on this board. It uses this "PICO RISC-V" (the entire CPU is in a single Verilog file): https://github.com/SymbiFlow/prjtrellis/tree/master/examples... I think it would be straightforward to build a Linux capable RISC-V system for this board using this free tool chain. The board has SDRAM, FTDI UART and SPI-flash. It does not have an SD slot, but maybe could be wired in with the expansion headers. This ULX3S board also looks promissing, b
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ut is not available yet: https://www.crowdsupply.com/radiona/ulx3s What's very cool is that low end ECP5 FPGAs are around $5. I think RISC-V on an ECP5 with LCD touch interface might be the cheapest available option for a Linux microcontroller with a touch LCD interface. By available, I mean where you can easily buy the chips on mainstream distributors (otherwise it would for sure be some AllWinner chip).
In RISC-V Stumbling Blocks
mrsteveman1·Jan 20, 2019
A few years ago that was true, and commercial tools are still horrid and closed and necessary for certain FPGA families. But as of right now you can use[1] the Lattice iCE40 (small, 8k LUTs), Lattice UltraPlus (5k LUTs, DSPs) and Lattice ECP5[2] (~85k LUTs, with 5G SerDes and PCIe Gen 2) with completely open tools. The ECP5 in particular would be well suited for it. And there is a productive effort[3] to do the same for the Artix-7 and other Xilinx 7 Series parts. Even for those parts that are still very much closed, you can load an existing bitstream on them using open tools. Intel Max10, which is the part found on the LimeSDR Mini, is one of those even though we don't have open bitstream documentation for it yet. The major commercial FPGA tools all work Linux at this point too, I use most of them on Ubuntu routinely including Lattice Di
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amond, Altera/Intel Quartus, and Xilinx ISE/Vivado. [1] http://www.clifford.at/icestorm/ [2] https://github.com/SymbiFlow/prjtrellis [3] https://github.com/SymbiFlow/prjxray
In Remotely compromise devices by using bugs in Marvell Avastar Wi-Fi

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