HackerReposA FIELD GUIDE TO OPEN SOURCE
ProSponsor the shelf♧ 0
← Back to top all-time
f4pga
prjxray
Python2018–2024
f4pga / prjxray

prjxray

Documenting the Xilinx 7-series bit-stream format.

12Distinct people
14Mentions
0Explicit recommenders
931GitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

Documenting the Xilinx 7-series bit-stream format.

GitHub

Where it is used

No documented product use was verified in the last source check.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

Mentioned in the same Hacker News threads. That is not proof they are substitutes.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:56:07 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year14 dated mentions

Observed mentions: 2018-05-13 12:44:08 UTC to 2024-01-04 21:03:38 UTC.

012342018-01-01 00:00:00 UTC to 2019-01-01 00:00:00 UTC (exclusive): 4 mentions; 1 submissions, 3 comments20182019-01-01 00:00:00 UTC to 2020-01-01 00:00:00 UTC (exclusive): 2 mentions; 0 submissions, 2 comments2020-01-01 00:00:00 UTC to 2021-01-01 00:00:00 UTC (exclusive): 2 mentions; 0 submissions, 2 comments2021-01-01 00:00:00 UTC to 2022-01-01 00:00:00 UTC (exclusive): 2 mentions; 0 submissions, 2 comments20212022-01-01 00:00:00 UTC to 2023-01-01 00:00:00 UTC (exclusive): 3 mentions; 0 submissions, 3 comments2023-01-01 00:00:00 UTC to 2024-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2024-01-01 00:00:00 UTC to 2025-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2024

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20182018-01-01 00:00:00 UTC2019-01-01 00:00:00 UTC413
20192019-01-01 00:00:00 UTC2020-01-01 00:00:00 UTC202
20202020-01-01 00:00:00 UTC2021-01-01 00:00:00 UTC202
20212021-01-01 00:00:00 UTC2022-01-01 00:00:00 UTC202
20222022-01-01 00:00:00 UTC2023-01-01 00:00:00 UTC303
20232023-01-01 00:00:00 UTC2024-01-01 00:00:00 UTC000
20242024-01-01 00:00:00 UTC2025-01-01 00:00:00 UTC101

What Hacker News says

14 sources
A bit of a nitpick - LiteX still mostly needs Vivado installed for now for 7 series FPGAs. There's a project that's very far along in reverse engineering the Xilinx bitstream (https://github.com/f4pga/prjxray), but it's still missing many features (PCIe, SERDES, hardware multipliers, etc.). You can run on the open source toolchain but you lose so many of the reasons to actually use a Xilinx FPGA. The only fully supported reverse engineered FPGAs at the moment are the Lattice ECP5(-5G), iCE40, and QuickLogic EOS families. https://f4pga.readthedocs.io/en/latest/status.html
In NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptop
this is true in general but 1) vivado webpack edition (ie free) lets you write (and flash) a bitstream for some of the small chips. i know it at least works for the artix-7 family because i'm doing it every day lately 2) for the artix-7 (and some lattice chips) you supposedly can use OSS (https://github.com/SymbiFlow/prjxray). i haven't tried it yet but one problem i can foresee is that the OSS tools won't infer stuff like brams and dsp. in fact the symbiflow people (i think?) explicitly call this out as the part of the project that's a work in progress. some useful links: https://arxiv.org/abs/1903.10407 https://github.com/YosysHQ/nextpnr https://www.rapidwright.io/
In AMD Receives Approval for Acquisition of Xilinx
In Symbiflow: The GCC of the FPGA World
> Maybe brave hackers will reverse engineer bitstream generation As far as I know, the bitstream for 15K/35K/50K Artix-7 is pretty much done, with Kintex-7 and Zynq devices being WIP [1]. I think there are gaps in support for the various hard blocks and PAR at higher layers of the toolchain, but the bitstream reverse engineering per se isn't a maybe-in-the-future thing. [1] https://github.com/SymbiFlow/prjxray
In Arduino MKR Vidor 4000 – Arduino, Cyclone 10 FPGA, MiniPCI Express, MicroHDMI
A few years ago that was true, and commercial tools are still horrid and closed and necessary for certain FPGA families. But as of right now you can use[1] the Lattice iCE40 (small, 8k LUTs), Lattice UltraPlus (5k LUTs, DSPs) and Lattice ECP5[2] (~85k LUTs, with 5G SerDes and PCIe Gen 2) with completely open tools. The ECP5 in particular would be well suited for it. And there is a productive effort[3] to do the same for the Artix-7 and other Xilinx 7 Series parts. Even for those parts that are still very much closed, you can load an existing bitstream on them using open tools. Intel Max10, which is the part found on the LimeSDR Mini, is one of those even though we don't have open bitstream documentation for it yet. The major commercial FPGA tools all work Linux at this point too, I use most of them on Ubuntu routinely including Lattice Di
Read the rest
In Remotely compromise devices by using bugs in Marvell Avastar Wi-Fi

MAKE YOURSELF AT HOME

A few shortcuts

/
Search the collection
?
Open this guide
Esc
Close dialogs and navigation

Your saved repositories and interests stay in this browser.