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OpenXiangShan
XiangShan
Scala2021–2026
OpenXiangShan / XiangShan

XiangShan

Open-source high-performance RISC-V processor

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14Distinct people
22Mentions
0Explicit recommenders
7.4KGitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

Open-source high-performance RISC-V processor

GitHub

Where it is used

No documented product use was verified in the last source check.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

Mentioned in the same Hacker News threads. That is not proof they are substitutes.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 5:04:57 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year22 dated mentions

Observed mentions: 2021-06-27 08:22:16 UTC to 2026-08-16 23:49:48 UTC.

024682021-01-01 00:00:00 UTC to 2022-01-01 00:00:00 UTC (exclusive): 3 mentions; 2 submissions, 1 comments20212022-01-01 00:00:00 UTC to 2023-01-01 00:00:00 UTC (exclusive): 2 mentions; 0 submissions, 2 comments2023-01-01 00:00:00 UTC to 2024-01-01 00:00:00 UTC (exclusive): 2 mentions; 1 submissions, 1 comments20232024-01-01 00:00:00 UTC to 2025-01-01 00:00:00 UTC (exclusive): 8 mentions; 0 submissions, 8 comments2025-01-01 00:00:00 UTC to 2026-01-01 00:00:00 UTC (exclusive): 4 mentions; 1 submissions, 3 comments2026-01-01 00:00:00 UTC to 2027-01-01 00:00:00 UTC (exclusive): 3 mentions; 0 submissions, 3 comments. Incomplete calendar period.2026*

* An incomplete calendar period is marked with an outlined bar. Its count is not directly comparable with a full period.

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20212021-01-01 00:00:00 UTC2022-01-01 00:00:00 UTC321
20222022-01-01 00:00:00 UTC2023-01-01 00:00:00 UTC202
20232023-01-01 00:00:00 UTC2024-01-01 00:00:00 UTC211
20242024-01-01 00:00:00 UTC2025-01-01 00:00:00 UTC808
20252025-01-01 00:00:00 UTC2026-01-01 00:00:00 UTC413
2026 (partial)2026-01-01 00:00:00 UTC2027-01-01 00:00:00 UTC303

What Hacker News says

22 sources
camel-cdr·Feb 3, 2025
XuanTie open sourced their C910 [1] and C906 core [2], excluding the xtheadvector support. You can get SBCs with them for quite cheap: C910: Lichee Pi 4A, C906: MangoPi Mq pro How much of the implementation used in actual silicon overlap with their open source cores isn't clear. I was able to figure out where some non-standard CSR bits are located [3]. Personal, I wouldn't recommend buying them, especially not because they are open source. While source code has been published, the source code looks partially generated and at least for a software dev like me, very hard to read. I would recommend waiting for the RuyiBook [4], which will contain the second generation of the OpenXiangShan core [5], which is developed fully in the open on GitHub. From the information available, it seems likely that it will become available this year and that i
Read the rest
t would then be the highest performing RISC-V processor generally available. See my old comment for benchmarks I ran in the RTL simulation: https://news.ycombinator.com/item?id=41331786#41331968 The only unfortunate thing it that it will likely lack support for the vector extension. I hope they follow my suggestion of shipping the processor source code with the default Linux install. [1] https://github.com/T-head-Semi/openc910 [2] https://github.com/XUANTIE-RV/openc906 [3] https://github.com/camel-cdr/rvv-d1?tab=readme-ov-file#enabl... [4] https://milkv.io/ruyibook [5] https://github.com/OpenXiangShan/XiangShan See also, slides on the XiangShanV2 microarchitecture: https://raw.githubusercontent.com/OpenXiangShan/XiangShan-do...
In Ask HN: Are there any open source RISC-V processors that I can buy and use?
camel-cdr·Oct 23, 2024
Meanwhile, I ran right now git clone an open-source high performance out-of-order RISC-V implementation simulate the RTL, and have it out perform my current destop cpu (Zen1) on a per cycle basis: https://camel-cdr.github.io/rvv-bench-results/articles/xperm... (scroll to bottom and compare scalar performance between Ryzen 1600x and XiangShanV3) You may notice that while scalar is faster, the vector performance is slower, this is because their vector implementation is still quite new, and they are still missing a few optimizations. XiangShan repo: https://github.com/OpenXiangShan/XiangShan More micro architectural details: https://www.servethehome.com/xiangshan-high-performance-risc... BTW, XiangShanV2 has already been taped out and will be available in an laptop in the future: https://milkv.io/ruyibook
In RISC-V is currently slow compared to modern CPUs
camel-cdr·Aug 23, 2024
Link to the open-source processor implementation: https://github.com/OpenXiangShan/XiangShan/tree/nanhu You can download and simulate it on regular hardware. I ran a few micro benchmarks it XiangShanV2 (Nanhu, the one in the laptop) and XiangShanV3 the next generation of their implementation: integer micro benchmark from the XiangShan repo: Zen1 1600x XiangShanV2 XiangShanV3 Quick sort: 16833 cycles 11122 cycles 10582 cycles Queen placement: 56606 cycles 59712 cycles 49912 cycles Brainf**k interpreter: 132821 cycles 113686 cycles 52676 cycles Fibonacci number: 7473 cycles 5999 cycles 2763 cycles Eratosthenes sieve: 5364 cycles 3140 cycles 2037 cycles A* 15-puzzle search: 20459 cycles
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14626 cycles 11018 cycles Dinic's maxflow algorithm: 12357 cycles 11184 cycles 6174 cycles Lzip compression: 7140 cycles 5932 cycles 2289 cycles Suffix sort: 16316 cycles 14967 cycles 11256 cycles MD5 digest: 5882 cycles 3793 cycles 1997 cycles Total: 281251 cycles 244161 cycles 150704 cycles scalar fp32 mandelbrot 64x64 with 64 iterations: Zen1 1600x: 1264882 cycles XiangShanV2: 1361856 cycles XiangShanV3: 1011363 cycles The Ryzen 1600X is my current desktop and the computer I ran the RTL simulation on. At the same clock frequency XiangShanV2 is quite competitive with the Zen1 CPU, however it doesn't implement the RISC-V vector extension, so will be a lot slower in any SIMD workloads. The RuyiBook is supposed to clock at 2.5GHz, but there were slides saying it can go up to 2.8GHz, while the 1600X can go up to 3.7GHz. XiangShanV3 is a lot faster, and does implement the RISC-V vector extension, as well the hypervisor extension. They also target a 3GHz frequency. Here is a recent presentation of XiangShanV2 micro architectural implementation details: https://raw.githubusercontent.com/OpenXiangShan/XiangShan-do... There were a few talks at RISC-V Summit Chine regarding XiangShanV3 implementation details. Here is a recording, look at the second Day 2, if the clunky interface works for you: https://www.c114.com.cn/live/t850.html They also present at this years hotchips in a few days.
In RuyiBook the first laptop powered by a open-source RISC-V processor
omniwrench·Apr 24, 2024
> I'm pretty sure that SiFive isn't allowed to sell their RISC-V core designs to any Chinese company already. The JH7110 SoC from the Chinese firm Starfive uses SiFive's U74 core. Eswin, also Chinese uses SiFive's P550 core in their upcoming EIC7700 SoC. > All Chinese RISC-V core designs have been proprietary designs thus far. There is the OpenC910 [1] and OpenXiangShan [2]. [1] https://github.com/T-head-Semi/openc910 [2] https://github.com/OpenXiangShan/XiangShan
In US Government reportedly ponders crimping China's use of RISC-V
camel-cdr·Jan 20, 2024
> Certainly no RISC-V implementations that are in the hands of customers right now do any fusion and it doesn't seem to hurt their ability to match or exceed the performance of similar Arm cores (A55, A72). You can play around with OpenXianShan though, they have a few fusion targets: https://github.com/OpenXiangShan/XiangShan/blob/master/src/m... Most of the targets require the same destination, so it won't be able to fuse current codegen. I suppose there is still some time before compilers need to be ready, but it's not that much. > Perhaps they will provide compiler patches if required. I hope so, btw t-head seems to be still be trying to upstream XTheadVector: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/64278...
In MRISC32 – An Open 32-Bit RISC/Vector ISA (Suitable for FPGA CPU)

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