openc910

Well, because there are open-source designs they'd be using. The GD32V microcontroller, for example, uses Nucleisys's BumbleBee, and high-performance chips from several vendors use Brother Honey Badger's Apache-licensed XuanTie C910: https://github.com/XUANTIE-RV/openc910 But see https://news.ycombinator.com/item?id=44503847

https://github.com/XUANTIE-RV/openc910/issues/9 Vperl, apparently

Quite likely, yes. It should be possible to make estimates of how much your cache misses are going to impact speed. But there's a tradeoff. It looks like they've chosen small area/low power over absolute speed. Which may be entirely valid for whatever use case they're aiming at. Note from the git history is that this is basically a 2021 design. https://github.com/XUANTIE-RV/openc910/commits/main/

Apache-2 open source: https://github.com/XUANTIE-RV/openc910

XuanTie open sourced their C910 [1] and C906 core [2], excluding the xtheadvector support. You can get SBCs with them for quite cheap: C910: Lichee Pi 4A, C906: MangoPi Mq pro How much of the implementation used in actual silicon overlap with their open source cores isn't clear. I was able to figure out where some non-standard CSR bits are located [3]. Personal, I wouldn't recommend buying them, especially not because they are open source. While source code has been published, the source code looks partially generated and at least for a software dev like me, very hard to read. I would recommend waiting for the RuyiBook [4], which will contain the second generation of the OpenXiangShan core [5], which is developed fully in the open on GitHub. From the information available, it seems likely that it will become available this year and that i

Not noted here is that the fastest RISC-V general purpose machines you can currently buy use the THead C910 core, which is: 1) Chinese 2) actually Open Source (except the vector unit): https://github.com/T-head-Semi/openc910 The fastest off the shelf RISC-V machine currently is the Milk-V Pioneer using the SG2042 SoC which has 64 C910 OoO cores running at 2.0 GHz, with 64 MB L3 cache and up to 128 GB RAM. The core, SoC, board, and PC are all made in China. Of course this situation changes very fast. There will be several machines using SiFive's P550 cores in several months -- most from Chinese companies, or at least using Chinese SoC (SiFive's own HiFive Premier P550 board). And then at the end of the year the Milk-V "Oasis" (and others from at least Sipeed) using SiFive's P670 cores, but again in the Chinese SG2380 SoC. There are a sever

> I'm pretty sure that SiFive isn't allowed to sell their RISC-V core designs to any Chinese company already. The JH7110 SoC from the Chinese firm Starfive uses SiFive's U74 core. Eswin, also Chinese uses SiFive's P550 core in their upcoming EIC7700 SoC. > All Chinese RISC-V core designs have been proprietary designs thus far. There is the OpenC910 [1] and OpenXiangShan [2]. [1] https://github.com/T-head-Semi/openc910 [2] https://github.com/OpenXiangShan/XiangShan

Seems really fake tbh: https://github.com/T-head-Semi/openc910

Note that the C910 CPU cores used in this chip are in fact open source: https://github.com/T-head-Semi/openc910 (C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)

More precisely, a Chinese university assembled a rack containing 48 [1] commercially available SBCs [2], each with a Chinese-designed and made SG2042 SoC with 64 C910 CPU cores. The C910 was designed in China in 2018/19 and open-sourced in October 2021, on Microsoft's github site. https://github.com/T-head-Semi/openc910 The SG2042 is the most powerful RISC-V SoC available today. In which direction is the technology transfer going? [1] or possibly 24 dual-socket boards, shown at the RISC-V Summit China in August [2] get your own here https://www.crowdsupply.com/milk-v/milk-v-pioneer

For "coming down the pipeline" they're essentially free. Today, the c910 is an Apache 2, hardware proven out of order core on GitHub here https://github.com/T-head-Semi/openc910 a little slower than an RPi3's core.

Here you go: https://github.com/T-head-Semi/openc910 (This isn't doesn't include the draft vector extension present in the C910)

Sorry if it’s a dumb question but how do you verify open source hardware? With software I have the code and I can build and deploy my own version. But how do you do that with an open source CPU? I can read the code [0] but will the CPU as the physical object itself be the same? And the microcode running inside? 0, https://github.com/T-head-Semi/openc910

Russia is not that great an example because they don't actually manufacture anything at all that we'd miss, and we can quickly get gas and oil from elsewhere (and have done so). The Chinese and US economies are far more inter-dependent and the Chinese understand that war is unthinkable -- are are very annoyed at Russia. The Western response to Ukraine has also put China off the notion that they could quietly take Taiwan without anyone making a fuss. But this is very far from RISC-V. China has long since (5+ years) taken everything from RISC-V initially done in the West that there is to take. The ISA specification itself, gcc and llvm and Linux and things like that. It is far too late to change that. They have local git clones. At present China is contributing more to RISC-V than anyone else. For example they are doing almost all work on A

Here is the source code* for the CPU: https://github.com/T-head-Semi/openc910 * AFAIK they didn't opensource the pre ratification vector extension implementation they ship with the taped out chip.