riscv-isa-sim

Spike, a RISC-V ISA Simulator

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REPOSITORY AT A GLANCE

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What it is

Spike, a RISC-V ISA Simulator

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

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Also in these discussions

thethirdone/rars · linked in 2 of the same discussions

Mentioned in the same Hacker News threads. That is not proof they are substitutes.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:56:07 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year4 dated mentions

Observed mentions: 2019-03-22 10:13:16 UTC to 2022-11-21 11:36:00 UTC.

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

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Period	Start (UTC)	End (exclusive, UTC)	Mentions	Comments
2019	2019-01-01 00:00:00 UTC	2020-01-01 00:00:00 UTC	2	2
2020	2020-01-01 00:00:00 UTC	2021-01-01 00:00:00 UTC	1	1
2021	2021-01-01 00:00:00 UTC	2022-01-01 00:00:00 UTC	0	0
2022	2022-01-01 00:00:00 UTC	2023-01-01 00:00:00 UTC	1	1

What Hacker News says

4 sources

YorkshireSeason·Nov 21, 2022

Nice work! How did you debug it? Did you run it against the 'official' RISC-V models Spike [1] or Sail [2]? [1] https://github.com/riscv-software-src/riscv-isa-sim [2] https://github.com/riscv/sail-riscv

In Show HN: Libriscv – RISC-V userspace emulator library

chrisseaton·Oct 17, 2020

You mean what physical machine should you use to teach yourself on? I wouldn't bother trying to use any physical hardware - use a simple command-line simulator https://github.com/riscv/riscv-isa-sim.

In Lecture notes on RISC-V assembly

thethirdone·Aug 4, 2019

There are several other simulators. For professional simulators working on software for RISC-V hardware there are Spike [0], rv8 [1], and QEMU [2] are popular. For educational purposes, Venus [3,4], RARS [5], and RIPES [6] are popular. A fuller list can be found at [7]. Disclaimer: I am the maintainer for RARS. I have my finger on the pulse of the education simulator scene so if you want a fuller list of educational simulators, I can wrangle those URLs. [0]: https://github.com/riscv/riscv-isa-sim [1]: https://github.com/rv8-io/rv8 [2]: http://git.qemu.org/qemu.git (upstream URL) [3]: https://github.com/kvakil/venus (original project) [4]: https://github.com/ThaumicMekanism/venus (currently maintained fork) [5]: https://github.com/TheThirdOne/rars [6]: https://github.com/mortbopet/Ripes [7]: https://riscv.org/software-status/

In Jupiter: RISC-V Assembler and Runtime Simulator

thethirdone·Mar 22, 2019

> maybe these could be in the README.md Currently there isn't a whole lot in the README; part of the goal of this post is to find questions that people would like answered in it. > Is an object file used for this or does the assembler just use the labels in the open files? The compilation is done entirely in memory and I don't recall any of the classes being analogous to a traditional object file. One of the things I would like to implement in the future is linking with ELF object files, and loading, executing and exporting ELF executables. However, that is a relatively big addition and I don't fully understand the ELF format. > Is there a list of the system calls you implement? I don't believe there is an easily accessible, static list. But RARS generates a list of available system calls accessible from the help menu. The classes for th

Read the rest

e system calls are all in this directory [0]. If its a supported system calls, its in that directory. > Did you follow an example or standard or did you just make up some system calls? In the translation from MARS, I kept a lot of the MARS/SPIM specific syscalls. However, to have at least a semblance of Linux (and with any other existing simulators) compatibility I implemented a few of the easy Linux system calls and remapped some of the MARS system call numbers to the ones used in Spike [1]. > Disclaimer: I'm no RISC-V expert and I didn't look at RARS for very long, so these might be stupid questions. No worries. I can't expect you to be an expert and these are very reasonable questions. Thanks for asking. [0]: https://github.com/TheThirdOne/rars/tree/master/rars/riscv/s... [1]: https://github.com/riscv/riscv-isa-sim

In Show HN: IDE for Learning RISC-V