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TheThirdOne
rars
Java2019–2025
TheThirdOne / rars

rars

RARS -- RISC-V Assembler and Runtime Simulator

2Distinct people
11Mentions
0Explicit recommenders
1.7KGitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

RARS -- RISC-V Assembler and Runtime Simulator

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

Mentioned in the same Hacker News threads. That is not proof they are substitutes.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:03:16 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year11 dated mentions

Observed mentions: 2019-03-21 22:08:03 UTC to 2025-10-28 05:37:37 UTC.

02462019-01-01 00:00:00 UTC to 2020-01-01 00:00:00 UTC (exclusive): 6 mentions; 3 submissions, 3 comments20192020-01-01 00:00:00 UTC to 2021-01-01 00:00:00 UTC (exclusive): 3 mentions; 0 submissions, 3 comments2021-01-01 00:00:00 UTC to 2022-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2022-01-01 00:00:00 UTC to 2023-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments20222023-01-01 00:00:00 UTC to 2024-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2024-01-01 00:00:00 UTC to 2025-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2025-01-01 00:00:00 UTC to 2026-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2025

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20192019-01-01 00:00:00 UTC2020-01-01 00:00:00 UTC633
20202020-01-01 00:00:00 UTC2021-01-01 00:00:00 UTC303
20212021-01-01 00:00:00 UTC2022-01-01 00:00:00 UTC000
20222022-01-01 00:00:00 UTC2023-01-01 00:00:00 UTC000
20232023-01-01 00:00:00 UTC2024-01-01 00:00:00 UTC101
20242024-01-01 00:00:00 UTC2025-01-01 00:00:00 UTC000
20252025-01-01 00:00:00 UTC2026-01-01 00:00:00 UTC101

What Hacker News says

11 sources
I'm not the person you asked, but I made an educational simulator for RISC-V [0]. The most critical resource even if it is not super convenient is the official RISC-V specification [1] (this is the latest draft as of writing this comment). There are a bunch of open source simulators [2] to look at for reference if you are unsure of how something is suppose to work. I would recommend compiling a C program to RISC-V and looking at disassembled machine code to get an idea for how things are normally done in terms of RISC-V assembly. There isn't any particularly nice documentation that I am aware of, but enough universities teach using it that there should be some resources that would be helpful for making a simulator. I can probably come up with some links if you are serious about making a simulator, but its a little too much effort to do fo
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In Implement an emulator for a fantasy CPU in JavaScript
> Mine currently passes the basic test suites The tests in riscv-tests are not complete enough to indicate strong compliance. I have found several bugs in my implementation that were not caught by them. > but it still fails in the C runtime startup when executing programs compiled with GCC The biggest issue I have seen with running C programs is that people don't have the system calls that C runs on startup. In a log from rv8, you need brk, uname, readlinkat, and mprotect. So without those you shouldn't be able to get a program into user code unless you make a custom entry point. Source: I am the maintainer of RARS (https://github.com/TheThirdOne/rars)
In Writing a RISC-V Emulator from Scratch
I wrote an educational simulator for RISC-V [0] two and a half years ago and the documentation for RISC-V has gotten marginally better. There a fair number of universities using RISC-V to teach that have published their slides and such publicly [1]. However those is not super helpful for people who already understand assembly and computer architecture reasonably well. The best way I can see to get up to speed is to read some example demonstrating each instruction. I have thought about a site that has a table of instructions that links to an online simulator [2] to let you step through an example detailing edge cases. The best source of simple assembly examples I know of would be the tests from my project [3]. Though those could be a lot more helpful for a human reading them. As for simulators, there are quite a few. The website lists a bu
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In RISC-V Stumbling Blocks

Ask HN: GitHub Repo SEO

I am looking for tips on how to help my project rank higher on Google and other search engines. From what I can tell it should be ranked similarly to other projects in the same space, but that isn't true. Specific Context: I am the author of RARS [0] and unless you search the name RARS, the github repo only shows up on the 3rd page or farther back on Google. The Google Summer of Code page [1] for the project and an HN submission [2] are generally higher ranked (especially when the keyword education is used). What confuses me is that other simulators Ripes [3] and Jupiter [4] (as of the HN post last week) routinely rank as 1st and 2nd spots for my test queries. In terms of stars, active users, and other such statistics, RARS appears to be superior. Venus [5] is used for CS61c at Berkeley and has probably the best educational material, but
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1 points · Open discussion
There are several other simulators. For professional simulators working on software for RISC-V hardware there are Spike [0], rv8 [1], and QEMU [2] are popular. For educational purposes, Venus [3,4], RARS [5], and RIPES [6] are popular. A fuller list can be found at [7]. Disclaimer: I am the maintainer for RARS. I have my finger on the pulse of the education simulator scene so if you want a fuller list of educational simulators, I can wrangle those URLs. [0]: https://github.com/riscv/riscv-isa-sim [1]: https://github.com/rv8-io/rv8 [2]: http://git.qemu.org/qemu.git (upstream URL) [3]: https://github.com/kvakil/venus (original project) [4]: https://github.com/ThaumicMekanism/venus (currently maintained fork) [5]: https://github.com/TheThirdOne/rars [6]: https://github.com/mortbopet/Ripes [7]: https://riscv.org/software-status/
In Jupiter: RISC-V Assembler and Runtime Simulator
> 1. How mature/stable is it? I'll have > 200 students, and if the tools I give them are buggy I'll have to deal with a complaint avalanche. (MARS is very stable.) As far as I am aware it is very stable. There were three slight bugs that I fixed after they were brought to my attention. #6, #7, #8 in the issue tracker [0]. There are some known bugs that are hard to fix, but I doubt any student would run into them as they all have to do with CSRs iirc or interrupts. I try to be pretty responsive about issues when they are brought up; if it were holding up a class, I would spend some time to fix the issue. And its possible that a motivated student would be able to fix the problem themselves. > 2. I want to build a test suite ... Is there any facility that allows me to use your simulator as a linkable library, rather than calling it from the
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command line? ... IIRC the command line wasn't significantly changed so your existing command line script should work. As for a linkable library, depending on what you are looking for that should be possible. It is possible that there is some global state which makes it hard to reset properly. When you say "linkable library" are you looking for a .jar with a clear api? Is the inconvenience just about not wanting to script in bash? Or is it about JVM startup time? I'll look into what it would take to make a easily configurable launch class. [0]:https://github.com/TheThirdOne/rars/issues
In Show HN: IDE for Learning RISC-V
> maybe these could be in the README.md Currently there isn't a whole lot in the README; part of the goal of this post is to find questions that people would like answered in it. > Is an object file used for this or does the assembler just use the labels in the open files? The compilation is done entirely in memory and I don't recall any of the classes being analogous to a traditional object file. One of the things I would like to implement in the future is linking with ELF object files, and loading, executing and exporting ELF executables. However, that is a relatively big addition and I don't fully understand the ELF format. > Is there a list of the system calls you implement? I don't believe there is an easily accessible, static list. But RARS generates a list of available system calls accessible from the help menu. The classes for th
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e system calls are all in this directory [0]. If its a supported system calls, its in that directory. > Did you follow an example or standard or did you just make up some system calls? In the translation from MARS, I kept a lot of the MARS/SPIM specific syscalls. However, to have at least a semblance of Linux (and with any other existing simulators) compatibility I implemented a few of the easy Linux system calls and remapped some of the MARS system call numbers to the ones used in Spike [1]. > Disclaimer: I'm no RISC-V expert and I didn't look at RARS for very long, so these might be stupid questions. No worries. I can't expect you to be an expert and these are very reasonable questions. Thanks for asking. [0]: https://github.com/TheThirdOne/rars/tree/master/rars/riscv/s... [1]: https://github.com/riscv/riscv-isa-sim
In Show HN: IDE for Learning RISC-V

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