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TheThirdOne
rars
Java2019–2025
TheThirdOne / rars

rars

RARS -- RISC-V Assembler and Runtime Simulator

2Distinct people
11Mentions
0Explicit recommenders
1.7KGitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

RARS -- RISC-V Assembler and Runtime Simulator

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

Mentioned in the same Hacker News threads. That is not proof they are substitutes.

This week on Hacker News

Nov 8–Nov 15 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/15/2026, 10:01:16 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year11 dated mentions

Observed mentions: 2019-03-21 22:08:03 UTC to 2025-10-28 05:37:37 UTC.

02462019-01-01 00:00:00 UTC to 2020-01-01 00:00:00 UTC (exclusive): 6 mentions; 3 submissions, 3 comments20192020-01-01 00:00:00 UTC to 2021-01-01 00:00:00 UTC (exclusive): 3 mentions; 0 submissions, 3 comments2021-01-01 00:00:00 UTC to 2022-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2022-01-01 00:00:00 UTC to 2023-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments20222023-01-01 00:00:00 UTC to 2024-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2024-01-01 00:00:00 UTC to 2025-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2025-01-01 00:00:00 UTC to 2026-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2025

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20192019-01-01 00:00:00 UTC2020-01-01 00:00:00 UTC633
20202020-01-01 00:00:00 UTC2021-01-01 00:00:00 UTC303
20212021-01-01 00:00:00 UTC2022-01-01 00:00:00 UTC000
20222022-01-01 00:00:00 UTC2023-01-01 00:00:00 UTC000
20232023-01-01 00:00:00 UTC2024-01-01 00:00:00 UTC101
20242024-01-01 00:00:00 UTC2025-01-01 00:00:00 UTC000
20252025-01-01 00:00:00 UTC2026-01-01 00:00:00 UTC101

What Hacker News says

3 sources
I'm not the person you asked, but I made an educational simulator for RISC-V [0]. The most critical resource even if it is not super convenient is the official RISC-V specification [1] (this is the latest draft as of writing this comment). There are a bunch of open source simulators [2] to look at for reference if you are unsure of how something is suppose to work. I would recommend compiling a C program to RISC-V and looking at disassembled machine code to get an idea for how things are normally done in terms of RISC-V assembly. There isn't any particularly nice documentation that I am aware of, but enough universities teach using it that there should be some resources that would be helpful for making a simulator. I can probably come up with some links if you are serious about making a simulator, but its a little too much effort to do fo
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In Implement an emulator for a fantasy CPU in JavaScript
> Mine currently passes the basic test suites The tests in riscv-tests are not complete enough to indicate strong compliance. I have found several bugs in my implementation that were not caught by them. > but it still fails in the C runtime startup when executing programs compiled with GCC The biggest issue I have seen with running C programs is that people don't have the system calls that C runs on startup. In a log from rv8, you need brk, uname, readlinkat, and mprotect. So without those you shouldn't be able to get a program into user code unless you make a custom entry point. Source: I am the maintainer of RARS (https://github.com/TheThirdOne/rars)
In Writing a RISC-V Emulator from Scratch
I wrote an educational simulator for RISC-V [0] two and a half years ago and the documentation for RISC-V has gotten marginally better. There a fair number of universities using RISC-V to teach that have published their slides and such publicly [1]. However those is not super helpful for people who already understand assembly and computer architecture reasonably well. The best way I can see to get up to speed is to read some example demonstrating each instruction. I have thought about a site that has a table of instructions that links to an online simulator [2] to let you step through an example detailing edge cases. The best source of simple assembly examples I know of would be the tests from my project [3]. Though those could be a lot more helpful for a human reading them. As for simulators, there are quite a few. The website lists a bu
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In RISC-V Stumbling Blocks

MAKE YOURSELF AT HOME

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