riscv-boom

You should checkout Chisel. https://chisel.eecs.berkeley.edu/ Its a HDL in Scala. It used extensively by Berkeley for things like the Open-Source RISC-V Rocket and Boom SoC chips. There are lots of projects based on it and you have some of the best open-source cores implemented in it. See: - https://github.com/freechipsproject/rocket-chip - https://github.com/ucb-bar/riscv-boom

"BOOM" is the Berkeley Out-of-Order Machine RISC-V processor https://ucb-bar.github.io/riscv-boom/ https://github.com/ucb-bar/riscv-boom I believe this particular chip is a research chip, and the first time that BOOM has been taped out in real silicon. Other RISC-V chips are based on the simpler, in-order Rocket design (eg. SiFive's HiFive Unleashed FU540); or are completely custom designs (eg. the Western Digital 32 bit chips that will soon be appearing in a hard drive near you). Note that most Linux distros would not run on this chip out of the box, since the chip does not support the C-compressed extension. They would need to be recompiled. (Of course the chip being a research project and not generally available makes this rather theoretical)

Not sure if they've done a production run, but BOOM[1] has existed for a while. I'm not sure if it supporst speculative execution yet. [1] https://github.com/ucb-bar/riscv-boom

> No announced RISC-V silicon is susceptible Wasn't the BOOM CPU (https://github.com/ucb-bar/riscv-boom) fabricated? It definitely seems vulnerable to Spectre.

Chisel has better type safety than Verilog yet it's much less verbose than VHDL. Verilog is the industrial language of choice at most ASIC shops, and there are things like VerilogAMS (mixed signal) and SystemVerilog (validation) that will keep it entrenched for a long time. If you didn't have to care about ecosystem, my amateur opinion is that Chisel > VHDL > SystemVerilog > Verilog. I wasn't sure how seriously to take Chisel until I saw the RISC-V BOOM definition https://github.com/ucb-bar/riscv-boom. It's clean, succinct, and I think Chisel is quite viable. It's also a testament to the symbolic nature of Scala. It holds together pretty well in JVM, ScalaJS, Chisel, and scala-native. Scala as a language is remarkably simple at the core, which Odersky does a good job of showing in his book, even though there are a lot of library feat

Nothing really new about this, the most relevant for most people is that Esperanto will hopefully put a lot of love into the open source BOOM repository. https://github.com/ucb-bar/riscv-boom That will help Open-Source projects such as LowRisc. http://www.lowrisc.org/

Maybe I'm missing the relevant nexus between Linux, Open Source, and RISC-V, but I'm pretty sure BOOM [1] was already running Linux ~2 years ago. [1] https://github.com/ucb-bar/riscv-boom

My understanding is, if the ISA is open, it's not nearly as important if the CPU design itself is not, because you can always choose another vendor. Having said that, there are open-source designs for RISC-V CPUs. If you have a FPGA lying around, you can compile BOOM [1] for it and have Linux running on that, although not at particularly impressive speeds of course. There's also lowRISC [2], which is working on a mass-produced development board with an open-source RISC-V CPU, in a format similar to a Raspberry PI. Their timeline says that they hope to be ready for crowd-funding the initial production run sometime this year. [1] https://github.com/ucb-bar/riscv-boom [2] http://www.lowrisc.org/

It's an instruction set architecture with different extensions, a "family" if you would. Just like ARM has 32-bit Cortex M0..M4 microcontrollers, as well as ARM64 with MMU and the works. These RISC-V silicon implementations on CrowdSupply are on the low end, RV32I (32-bits, integer-only). The SiFive one supports M (multiply) A (atomic) C (compressed, like Thumb for ARM) extensions. No, you cannot build a smartphone with these. But there are other implementations. An example high-end implementation, 64-bits (you cannot buy silicon yet, but maybe you can burn your own FPGA) is BOOM: https://github.com/ucb-bar/riscv-boom

I think we need to do more work to demonstrate the advantages of tagged memory to potential adopters. I hope that the cost/benefit ratio will be such that others will adopt it. As for other improvements, it's difficult to pick out specific projects. Off the top of my head, the work on an efficient out-of-order RISC-V core BOOM (https://github.com/ucb-bar/riscv-boom/) is exciting, peripherals such as USB or memory controllers are valuable, and there's a lot to be done in terms of benchmarking and performance analysis.

There is the Berkley Out of Order Machine BOOM https://github.com/ucb-bar/riscv-boom, its performance approaches those of modern intel processors in core mark, I think it would probably be possible to eventually match them.

RISC-V is an open source ISA: https://en.wikipedia.org/wiki/RISC-V It has a number of implementations, both fully open source ones (BSD licensed), and proprietary. This one is based on the open source Rocket Chip implementation (https://github.com/ucb-bar/rocket), which is a simple in-order design, something like ARM Cortex-M or Intel Atom. (There is also one open source out-of-order design called BOOM - https://github.com/ucb-bar/riscv-boom)

The really cool thing is that existing implementations of RISC-V microprocessors, like what Berkeley provides, rocket (https://github.com/ucb-bar/rocket) and boom (https://github.com/ucb-bar/riscv-boom), and lowRISC uses and modifies have a dedicated accelerator socket. We've have good luck developing software/hardware infrastructure for machine learning accelerators and interfacing an example multilayer perceptron backend with this infrastructure (with Linux integration ongoing). This work (shameless plug: https://github.com/bu-icsg/xfiles-dana) may provide a starting point, examples, or general guidance for developing machine learning or other accelerators in this space. But, I can't overemphasize how the ongoing work at Berkeley and lowRISC have facilitated this process.

It's great to see how RISC-V has stimulated a lot of activity in open source CPU design. There are a few implementations now: * Rocket https://github.com/ucb-bar/rocket-chip * lowRISC ASIC http://www.lowrisc.org/ * PicoRV32 https://github.com/cliffordwolf/picorv32 * BOOM (derived from Rocket) https://github.com/ucb-bar/riscv-boom * SODOR https://github.com/ucb-bar/riscv-sodor * VSCALE https://github.com/ucb-bar/vscale Anyone know of any more?

We already have a RISC-V superscalar out-of-order core, the Berkeley Out-of-Order Machine (BOOM). https://github.com/ucb-bar/riscv-boom