rocket

RISC-V is an open source ISA: https://en.wikipedia.org/wiki/RISC-V It has a number of implementations, both fully open source ones (BSD licensed), and proprietary. This one is based on the open source Rocket Chip implementation (https://github.com/ucb-bar/rocket), which is a simple in-order design, something like ARM Cortex-M or Intel Atom. (There is also one open source out-of-order design called BOOM - https://github.com/ucb-bar/riscv-boom)

It's actually a combination of public knowledge and trade secrets. The public knowledge comes from what the chip-makers themselves describe in conferences, trade journals, etc. Those would get you really far in design, implementation, and verification. There are also trade secrets for optimizing both digital and analog components. They stay trade secrets for the obvious reason of slowing competition but also to reduce odds of patent suits given about everything you can think of will get patented in this field. Especially micro-architecture tricks within CPU's. You can get much of the knowledge you need from books, CPU specs, academic papers, open-source CPU's in industry, and so on. The standard cell model is the easiest with the highest performers being full-custom designs. There are plenty of successful designs in former with good perfo

The really cool thing is that existing implementations of RISC-V microprocessors, like what Berkeley provides, rocket (https://github.com/ucb-bar/rocket) and boom (https://github.com/ucb-bar/riscv-boom), and lowRISC uses and modifies have a dedicated accelerator socket. We've have good luck developing software/hardware infrastructure for machine learning accelerators and interfacing an example multilayer perceptron backend with this infrastructure (with Linux integration ongoing). This work (shameless plug: https://github.com/bu-icsg/xfiles-dana) may provide a starting point, examples, or general guidance for developing machine learning or other accelerators in this space. But, I can't overemphasize how the ongoing work at Berkeley and lowRISC have facilitated this process.

Their github page is here (https://github.com/lowrisc). For example, here's the code to the Rocket processor (https://github.com/lowRISC/rocket), which is a fork from Berkeley's (https://github.com/ucb-bar/rocket).

The 2-4 main cores will be derived from the UC Berkeley Rocket core generator https://github.com/ucb-bar/rocket. Currently this is single issue, in-order though it is designed to be a dual-issue in-order core (i.e. superscalar).