riscv-boom

I think we need to do more work to demonstrate the advantages of tagged memory to potential adopters. I hope that the cost/benefit ratio will be such that others will adopt it. As for other improvements, it's difficult to pick out specific projects. Off the top of my head, the work on an efficient out-of-order RISC-V core BOOM (https://github.com/ucb-bar/riscv-boom/) is exciting, peripherals such as USB or memory controllers are valuable, and there's a lot to be done in terms of benchmarking and performance analysis.

There is the Berkley Out of Order Machine BOOM https://github.com/ucb-bar/riscv-boom, its performance approaches those of modern intel processors in core mark, I think it would probably be possible to eventually match them.

RISC-V is an open source ISA: https://en.wikipedia.org/wiki/RISC-V It has a number of implementations, both fully open source ones (BSD licensed), and proprietary. This one is based on the open source Rocket Chip implementation (https://github.com/ucb-bar/rocket), which is a simple in-order design, something like ARM Cortex-M or Intel Atom. (There is also one open source out-of-order design called BOOM - https://github.com/ucb-bar/riscv-boom)

The really cool thing is that existing implementations of RISC-V microprocessors, like what Berkeley provides, rocket (https://github.com/ucb-bar/rocket) and boom (https://github.com/ucb-bar/riscv-boom), and lowRISC uses and modifies have a dedicated accelerator socket. We've have good luck developing software/hardware infrastructure for machine learning accelerators and interfacing an example multilayer perceptron backend with this infrastructure (with Linux integration ongoing). This work (shameless plug: https://github.com/bu-icsg/xfiles-dana) may provide a starting point, examples, or general guidance for developing machine learning or other accelerators in this space. But, I can't overemphasize how the ongoing work at Berkeley and lowRISC have facilitated this process.

It's great to see how RISC-V has stimulated a lot of activity in open source CPU design. There are a few implementations now: * Rocket https://github.com/ucb-bar/rocket-chip * lowRISC ASIC http://www.lowrisc.org/ * PicoRV32 https://github.com/cliffordwolf/picorv32 * BOOM (derived from Rocket) https://github.com/ucb-bar/riscv-boom * SODOR https://github.com/ucb-bar/riscv-sodor * VSCALE https://github.com/ucb-bar/vscale Anyone know of any more?

We already have a RISC-V superscalar out-of-order core, the Berkeley Out-of-Order Machine (BOOM). https://github.com/ucb-bar/riscv-boom