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XUANTIE-RV
openc906
Verilog2022–2025
XUANTIE-RV / openc906

openc906

OpenXuantie - OpenC906 Core

4Distinct people
6Mentions
0Explicit recommenders
425GitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

OpenXuantie - OpenC906 Core

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

Mentioned in the same Hacker News threads. That is not proof they are substitutes.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 5:04:57 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year6 dated mentions

Observed mentions: 2022-03-15 21:10:17 UTC to 2025-02-03 19:38:10 UTC.

0122022-01-01 00:00:00 UTC to 2023-01-01 00:00:00 UTC (exclusive): 2 mentions; 0 submissions, 2 comments20222023-01-01 00:00:00 UTC to 2024-01-01 00:00:00 UTC (exclusive): 2 mentions; 0 submissions, 2 comments20232024-01-01 00:00:00 UTC to 2025-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2025-01-01 00:00:00 UTC to 2026-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2025

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20222022-01-01 00:00:00 UTC2023-01-01 00:00:00 UTC202
20232023-01-01 00:00:00 UTC2024-01-01 00:00:00 UTC202
20242024-01-01 00:00:00 UTC2025-01-01 00:00:00 UTC101
20252025-01-01 00:00:00 UTC2026-01-01 00:00:00 UTC101

What Hacker News says

6 sources
XuanTie open sourced their C910 [1] and C906 core [2], excluding the xtheadvector support. You can get SBCs with them for quite cheap: C910: Lichee Pi 4A, C906: MangoPi Mq pro How much of the implementation used in actual silicon overlap with their open source cores isn't clear. I was able to figure out where some non-standard CSR bits are located [3]. Personal, I wouldn't recommend buying them, especially not because they are open source. While source code has been published, the source code looks partially generated and at least for a software dev like me, very hard to read. I would recommend waiting for the RuyiBook [4], which will contain the second generation of the OpenXiangShan core [5], which is developed fully in the open on GitHub. From the information available, it seems likely that it will become available this year and that i
Read the rest
t would then be the highest performing RISC-V processor generally available. See my old comment for benchmarks I ran in the RTL simulation: https://news.ycombinator.com/item?id=41331786#41331968 The only unfortunate thing it that it will likely lack support for the vector extension. I hope they follow my suggestion of shipping the processor source code with the default Linux install. [1] https://github.com/T-head-Semi/openc910 [2] https://github.com/XUANTIE-RV/openc906 [3] https://github.com/camel-cdr/rvv-d1?tab=readme-ov-file#enabl... [4] https://milkv.io/ruyibook [5] https://github.com/OpenXiangShan/XiangShan See also, slides on the XiangShanV2 microarchitecture: https://raw.githubusercontent.com/OpenXiangShan/XiangShan-do...
In Ask HN: Are there any open source RISC-V processors that I can buy and use?
Most likely you have the mitigation already in place, that is disabeling the XTheadVector extension. The regular distributions don't enable it, since it's a non standard incompatible vendor extension based on a draft spec. When I wanted to benchmark their implementation last year I patched a kernel to enable it, and needed to consult the open source part of the core [0] to figure out that they placed the enable CSR bit in a different location than the final ratified spec. [1] [0] https://github.com/T-head-Semi/openc906 (doesn't include XTheadVector extension) [1] https://github.com/camel-cdr/rvv-d1
In Faulty instructions in C910 RISC-V CPUs
Here is what I found: Minimal Documentation: https://milkv.io/docs/duo/getting-started/cv1800b Datasheet: https://github.com/milkv-duo/hardware Reading the datasheet, it looks like there is one C906 cpu with 700 Mhz without the the vector extension and one C906 cpu at 1Ghz with rvv 0.7.1. The C906 design has been opensourced and is available here: https://github.com/T-head-Semi/openc906 The C906 supports rv64gc with optional rvv 0.7.1 with a vlen of 128, but a 256 wide ALU. They list H.264/H.265 support, but I don't think it's a standardized extension. But see my other comment about using the pre ratification vector extension: https://news.ycombinator.com/item?id=36377439#36378911
In Milk-V Duo: A $9 RISC-V Computer

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