firrtl

Speaking about design challenges - it would be nice if industry will switch to LLVM-like low-level HDL (or RTL) language, that will allow easier cross-tool integration. So far every project implements everything itself. There is an idea[1] to adapt FIRRTL[2][3] for this needs. Here is a good paper[4] describing its features. Apparently Intel also using it, at least in the research labs. This will help to integrate all parts of FPGA and ASIC design pipeline together. For now chip-design feels like programming in 1990 - quality of tooling is very bad. [1] https://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/freechipsproject/FIRRTL [4] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/...

A bit of unrelated, but since it is important for chips development posting it here. There is an initiative [1] to make FPGA/ASIC design tooling more universal and interconnected with sharing the LLVM-like low level intermediate representation (HDL), which is more powerful than Verilog or VHDL. At this point many people see FIRRTL[2][3] as a viable candidate for this position, with some enhancements. [1] https://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/freechipsproject/FIRRTL